        set no_route ""
        set DEVICE "AGRV2KL64"
        set TOP_MODULE "pll"
        set verilog pll.vo
        set DESIGN pll
        set sdc "a.sdc"
        set ta_report_auto 1
        set RESULT_DIR "."
        set RESULT $DESIGN
        eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000"
        # 以下命令是mode==QUARTUS ,mode只能二选一
        set ret [read_design_and_pack -sdc $sdc  -top ${TOP_MODULE} $verilog]
        # 以下命令是mode==SYNPLICITY | NATIVE
        set ret [read_design -top ${TOP_MODULE}  $verilog -hierachy 1 -pack q.txt]

        # 当执行到此处是. 有关时钟等问题就出现了,可以看出gclk是引用gnd~I,还是clkout

        set FITTER hybrid
        # set_mode -effort highest
        # set_mode -skew basic
        # set_mode -holdx default
        source "./${DESIGN}.asf"

        set ret [place_pseudo -user_io -place_io -place_pll -place_gclk -warn_io]
        if { !$ret } { exit -1 }

        set seed_rand ""
        set RETRY 0
        # set org_place "-org_place"
        # set load_place "-load_place"
        # set load_route "-load_route"
        set org_place ""
        set load_place ""
        set load_route ""
        set quiet ""
        eval "place_and_route_design $org_place $load_place $load_route \
                                    -retry $RETRY $seed_rand $quiet"


        # report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz
        # report_timing -verbose 2 -setup -brief -file $::alta_work/setup_summary.rpt.gz
        # report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz
        # report_timing -verbose 2 -hold -brief -file $::alta_work/hold_summary.rpt.gz

        # set ta_report_auto_constraints 0
        # report_timing -fmax -file $::alta_work/fmax.rpt
        # report_timing -xfer -file $::alta_work/xfer.rpt
        # set ta_report_auto_constraints $ta_report_auto

        # #set ta_coverage_limit "0.95 0.90"
        # set ta_dump_uncovered 1
        # report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz
        # #unset ta_coverage_limit
        # unset ta_dump_uncovered
        # set rt_report_timing_fast false

        # 以下命令是写入最终布线的v文件. 可以查看布线规则 (如gclk是否引用gnd~I,还是clkout)
        write_routed_design "${RESULT_DIR}/${RESULT}_routed.v"
        date_time

        bitgen normal -prg "${RESULT_DIR}/${RESULT}.prg" -bin "${RESULT_DIR}/${RESULT}.bin"
        bitgen sram -prg "${RESULT_DIR}/${RESULT}_sram.prg"
        bitgen download -bin "${RESULT_DIR}/${RESULT}.bin" -svf "${RESULT_DIR}/${RESULT}_download.svf"
        generate_binary -slave "${RESULT_DIR}/${RESULT}_slave.rbf" \
                        -inputs "${RESULT_DIR}/${RESULT}.bin" -reverse
        generate_binary -master "${RESULT_DIR}/${RESULT}_master.bin" \
                        -inputs "${RESULT_DIR}/${RESULT}.bin"
        generate_programming_file "${RESULT_DIR}/${RESULT}_master.bin" -prg "${RESULT_DIR}/${RESULT}_master.prg" \
        -as "${RESULT_DIR}/${RESULT}_master_as.prg" -hybrid "${RESULT_DIR}/${RESULT}_hybrid.prg"